IK: There are n Iks with k=1, 2, 3, …, n. IK is the comparator of kth input of the IADC. Each IK has two (2) inputs. First input is the kth input analog signal after sample and hold, i.e. Ak. Second input is the output of the DAC of the IADC i.e. AD. Each IK has four (4) binary outputs in the form of four flags LK, HK, FK, and PK.
LK flag output of IK will be set for Ak>AD-ε, where ε is noise margin of input analog signal. LK ascertains that Ak is greater than lower limit of AD. For ε=0, Lk and HK flags merge with same value. (k=1,2,…,n)
HK flag output of IK will be set for Ak>AD+ε. HK ascertains that Ak is greater than higher limit of AD. (k=1,2,…,n)
FK flag output of IK will be set for AD+ε≥Ak≥AD-ε. For FK=1 search for input Ak is taken as complete and corresponding output digital register RK is set with the value present in RD. (k=1,2,…,n)
PK flag output of IK is set for Ak≤AD-ε. For ε=0 this condition changes to Ak
RK is q-bit binary register to store output equivalent to kth input.
RD is q-bit binary register input to the DAC.
RDC is q-bit binary register to store the value of RD at COP.
q-bit DAC is the digital to analog converter to generate test point for the search algorithm.
X is q-bit binary register to earmark approximation point – only 1-bit remains set (1) at any time.
XC is q-bit binary register to store the value of X at COP.
IBS Logic is the digital logic circuit to perform IBS to generate digital equivalents to analog inputs AKs that are to be stored in RKs. In other words IBS is designed to store and perform the microprogramming for the microarchitecture of the IADC.
Invention Title: Interlaced Analog to Digital Conversion (IADC)>>
Invention Theme: Parallel I/O A/D Converter Using 1 D/A Converter.>>
Invention Aim: Improvement of Successive Approximation A/D Converter (SADC)Using Time Division Multiplexing (TDM).>>
Invention Algorithm: Interlaced Binary Search Algorithm (IBS).>>
Invention Advantage: Simultaneous Multiple Items Search in Binary Search Tree.>>
Refer>>> http://alokeinweb.googlepages.com/interlacedadconverter
The problem to be solved:
The invention is removing drawbacks of successive approximation analog to digital (A/D) converter (SADC) that uses one digital to analog (D/A) converter, time division multiplexing (TDM) and binary search algorithm to convert multiple analog inputs to digital equivalent. Drawbacks are (1) due to log(n) limit of binary searching time, input signal variation rate and leakage in S&H (sample and hold) circuits total number of inputs is limited to a low value and (2) S&H circuits require high synchronised clock signal.
Description:
The invention, Interlaced Analog to Digital (IADC) uses 1 D/A converter similar to SADC but reads simultaneously all inputs instead of TDM. IADC uses Interlaced Binary Search (IBS) algorithm that is the base invention by me. IBS removes drawbacks of binary search that are inability to search multiple items simultaneously and log2n search efficiency limit. IADC will fit in applications that requires simultaneous multiple analog to digital conversions.
ANOTHER USE OF IBS: ENCRYPTION OF BINARY DATA ON SIMULATANEOUS SEARCH OF MULTIPLE ITEMS ON A BINARY SEARCH TREE (encode a group of bits using lesser number of bits) refer:http://www.freepatentauction.com/patent.php?nb=3135
Presentation:
IADC is a modification of SADC. IADC requires 1 D/A converter, n sample and hold (S/H) circuits without TDM but simultaneous S/H, n q-bit output binary registers (q is resolution of IADC), 4n binary flags, 4 q-bit binary registers ( 1 for D/A converter input and 3 for intermediate data hold register) and IBS logic circuit.
Advantages:
IADC will reduce total number of A/D converters that uses successive approximation and TDM to convert a lot of analog signals to digital equivalents. IADC will fit in applications that requires simultaneous multiple analog to digital conversions.
Crirical Advantage of IADC over SADC: Besides overall advantage of IADC that is simultaneous high efficiency search of multiple items in a binary search tree The key advantage is “If input analog values are either 'closely spaced' or 'reside in leaves of the binary search tree' or combination of these two the search effiency will increase a lot.” So appropriate scaling of input values will bring high efficiency in IADC implementation. This will resemble to parallel conversions of all inputs through parallel SADCs - 1 SADC per input.
Application:
Electronics & Communication Engg. Replacement of A/D converter using TDM. Special note to process control instrumentation. Also the algorithm IBS has another application of data encoding (patent pending).
More Information
Development Status: Rough Prototype International Patents: India Patent NO. 221740
